The Chair for Operating Systems (Univ.-Prof. Dr. habil. Th. Bemmerl) provides the following
Bachelor Thesis (Bachelorarbeit) in the range of
Parallel Many-core Computing:
Evaluation of the SCC’s Power Management Capabilities
Background
The Intel Single-Chip Cloud Computer (SCC) experimental processor is a 48-core concept vehicle created by Intel Labs as a platform for Many-core software research.
The 48 cores are arranged in a 6x4 on-die mesh of tiles with two cores per tile.
The SCC chip possesses four on-die memory controllers for addressing the external main memory.
Additionally, each tile possesses a small amount of fast on-die memory that is also accessible to all other cores in a shared-memory manner. These special memory regions are the so-called Message-Passing Buffers (MPBs) of the SCC.
Within parallel applications, waiting for a message means either blocking inside a system call or polling, for example, on a spinlock.
In the former case, the OS-related overhead of unblocking and rescheduling usually increases the message latency, whereas the second case results in cycle-consuming busy waiting.
Thus, if a system should offer low-latency as well as power-awareness, it has to take care of an appropriate cycle frequency during busy waiting on its own.
The SCC exhibits both a low-latency communication infrastructure and low-latency power management facilities.
Therefore, the SCC is the ideal target platform for evaluating the achievable energy conservation representative for future Many-core systems.
Assignment
- Analysis of the SCC’s power management facilities
- Implementing a power-aware message scheduler
- Evaluation of the actually achievable energy conservation
We offer
- Comfortable working environment
- A good equipped computer infrastructure
- Access to an Intel Single-Chip Cloud Computer
- Personal and engaged supervision
Profile of requirements
- Prerequisites for starting a Bachelor's thesis
- Good programming skills in C/C++
- Competence to work autonomous and creative
Contact
Dr. rer. nat. Stefan Lankes
Lehrstuhl für Betriebssysteme (LfBS), RWTH Aachen
Kopernikusstraße 16, D-52056 Aachen
Tel.: +49 241 80 27609, Fax: +49 241 80 627634
E-Mail: lankes@lfbs.rwth-aachen.de | 
