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The Intel Single-Chip Cloud Computer (SCC)

The Intel Single-Chip Cloud Computer (SCC)

(image origin: Intel)

With the Intel Single-chip Cloud Computer as a prototype for future many-core processors, researchers have even today the opportunity to investigate the requirements of tomorrow's software design and programming models. The chair for operating systems is member of the Many-core Applications Research Community .

SCC is a research platform that contains a many-core research processor with 48 non-coherent memory-coupled cores and represents a very recent example for a Cluster-on-Chip architecture. All 48 cores are arranged in a 6x4 on-die mesh of tiles with two cores per tile on a single chip accompanied by four on-die DDR3 memory controllers to address the main memory. Additionally, each tile possesses a small amount of fast on-die memory that is also accessible to all other cores in a shared-memory manner. These special memory regions are the so-called Message-Passing Buffers.

Our current research project MetalSVM targets a shared virtual memory system for the SCC. Using the current SCC configuration one instance of an operating system runs per core using the shared main memory in a strict manner. In addition to that partitioned way of use, it is possible to access shared main memory in an unsplit and concurrent manner. Because of a missing coherence in hardware, the software in terms of a bare metal hypervisor has to take this part and guarantee coherence to the shared memory application. Here, we investigate the use of SCC related features like the on-die Message-Passing Buffers for a fast communication between the cores. MetalSVM is implemented in terms of a bare-metal hypervisor, located within a virtualization layer between the SCC's hardware and the actual operating system. The hypervisor handles the task of coherency management using different synchronization strategies.

SCC-MPICH is a SCC-customized MPI Library that is developed and maintained by the Chair for Operating Systems. Intel provides with RCCE a customized message-passing library for the SCC that utilizes the fast on-die Message-Passing Buffers. This library offers an application programming interface (API) with a semantics that is derived from the well-established MPI Standard. In contrast to the very broad range of functions of the MPI standard, Intel's API is kept very small by intention and doesn't offer all features of the MPI standard. In the context of a further research project that deals with the challenges of message-passing in future Many-core systems, we have implemented the MPI library SCC-MPICH, which in turn is based on an extension of Intel's RCCE library called iRCCE.

We believe that the investigation and implementation results of our SCC-related research projects will turn out to be very beneficial for future developments in the Many-core area.