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The Intel Single-Chip Cloud Computer (SCC)

A Bare-Metal Hypervisor for Non-Coherent Memory-Coupled Cores

On a traditional multicore system, a single operating system manages all cores and schedules threads and processes among them, inherently supported by hardware-implemented cache coherence protocols. However, a further growth of the number of cores per system implies an increasing chip complexity, especially with respect to the cache coherence protocols. Therefore, a very attractive alternative for future many-core systems is to waive the hardware-based cache coherency and to introduce a software-oriented message-passing based architecture instead: a so-called Cluster-on-Chip architecture.

Intel's Single-Chip Cloud Computer (SCC) , a many-core research processor with 48 non-coherent memory-coupled cores, is a very recent example for such a Cluster-on-Chip architecture. The SCC can be configured to run one operating system per core by partitioning the shared main memory in a strict manner. However, it is also possible to access the shared main memory in an unsplit and concurrent manner, provided that the cache coherency is then ensured by software.

Research Objective

In this project, we develop a new approach for a SCC-related shared virtual memory management system, called MetalSVM, that will be implemented in terms of a bare-metal hypervisor, located within a virtualization layer between the SCC's hardware and the actual operating system. This new hypervisor will undertake the crucial task of coherency management by utilizing special SCC-related features as, for example, its on-die Message-Passing Buffers (MPB). That way, common Linux kernels will be able to run almost transparently across the entire SCC system. However, in order to offer a maximum of flexibility with respect to resource allocation as well as to an efficiency-adjusted degree of parallelism, also a dynamic partitioning of the SCC's computing resources into several coherency domains will be made possible.

MetalSVM related Publications:

S. Lankes, P. Reble:
[bib] [url]
MetalSVM: Integration of Shared Virtual Memory Management to a Bare-Metal Hypervisor for future Many-core Processors (Poster Paper)
In 5th USENIX Workshop on Hot Topics in Parallelism (HotPar 13), San Jose, CA, USA, June 2013

P. Reble, J. Galowicz, S. Lankes, T. Bemmerl:
[bib] [url]
Efficient Implementation of the bare-metal hypervisor MetalSVM for the SCC
In Proceedings of the 6th Many-core Applications Research Community (MARC) Symposium, Toulouse, France, July 2012

P. Reble, S. Lankes, F. Zeitz, T. Bemmerl:
[bib] [url]
Evaluation of Hardware Synchronization Support of the SCC Many-Core Processor (Poster Paper)
In 4th USENIX Workshop on Hot Topics in Parallelism (HotPar 12), Berkeley, CA, USA, June 2012

S. Lankes, P. Reble, C. Clauss, O. Sinnen:
[bib] [url]
Revisiting Shared Virtual Memory Systems for Non-Coherent Memory-Coupled Cores
In Proceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM 2012) in conjunction with the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2012), New Orleans, LA, USA, February 2012

S. Lankes, P. Reble, C. Clauss, O. Sinnen:
[bib] [pdf]
The Path to MetalSVM: Shared Virtual Memory for the SCC (Belonged to the Winner of the Best Paper Award - 2nd Place)
In Proceedings of the 4th Many-core Applications Research Community (MARC) Symposium, Potsdam, Germany, December 2011

P. Reble, S. Lankes, C. Clauss, T. Bemmerl:
[bib] [pdf]
A Fast Inter-Kernel Communication and Synchronization Layer for MetalSVM (Belonged to the Winner of the Best Paper Award - 2nd Place)
In Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium, Ettlingen, Germany, July 2011

MetalSVM related Talks:

15th May 2013, 15:10, Invited talk at parallel 2013, Karlsruhe, Germany
A Life without Cache Coherency - A triennial Experiment on Oneself
Stefan Lankes, Carsten Clauss, RWTH Aachen University

20th July 2012, 10:00, MARC Symposium 2012, ONERA, Toulouse, France, July 2012
Efficient Implementation of the bare-metal hypervisor MetalSVM for the SCC
Jacek Galowicz, RWTH Aachen University

23rd March 2012, 11:00, Invited Talk at the University of Auckland, New Zealand
Bare Metal Programming for Future Many Core Architectures
Pablo Reble, RWTH Aachen University

9th November 2010, 10:00, Invited talk at the 1st MARC Symposium 2010, Braunschweig, Germany
First Experiences with SCC and a Comparison with Established Architectures
Stefan Lankes, RWTH Aachen University



This research project is funded by Intel Corporation.