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The Intel Single-Chip Cloud Computer (SCC)

A Power-Aware, Low-Latency MPI Implementation for the Intel SCC

The Intel Single-Chip Cloud Computer (SCC) experimental processor is a 48-core concept vehicle created by Intel Labs as a platform for many-core software research. The 48 cores are arranged in a 6x4 on-die mesh of tiles with two cores per tile. The SCC chip possesses four on-die memory controllers for addressing the external main memory. Additionally, each tile possesses a small amount of fast on-die memory that is also accessible to all other cores in a shared-memory manner. These special memory regions are the so-called Message-Passing Buffers (MPBs) of the SCC.

The SCC's architecture does not provide any cache coherency between the cores, but rather offers a low-latency infrastructure in terms of these MPBs for explicit message-passing between the cores. Thus, the processor resembles a Cluster-on-Chip architecture with distributed but shared memory where each core can run its own operating system instance. Communication between processes hosted by different OS instances running on different cores can then be conducted either via a dedicated region of the off-die shared memory or via the fast on-die MPBs for increased performance.

Research Objective

Our research objective focuses on the development of a high-performance message-passing library (according to the MPI standard) that is able to minimize the CPU-related energy consumption of parallel applications.

Within common MPI-implementations, waiting for a message means either blocking inside a system call or polling, for example on a spinlock. In the former case, the OS-related overhead of unblocking and rescheduling usually increases the message latency, whereas the second case results in cycle-consuming busy waiting. Thus, if an MPI library should offer low-latency as well as power-awareness, it has to take care of an appropriate cycle frequency during busy waiting on its own.

The SCC exhibits both a low-latency communication infrastructure and low-latency power management facilities. Therefore, the SCC is the ideal target platform for prototyping such an MPI library and for evaluating the achievable energy conservation representative for real-world MPI applications on future Many-core systems.

SCC-MPICH related Publications

P. Reble, C. Clauss, M. Riepen, S. Lankes, T. Bemmerl:
[bib] [pdf]
Connecting the Cloud: Transparent and Flexible Communication for a Cluster of Intel SCCs (Belonged to the Winner of the Best Paper Award - 2nd Place)
In Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH, Aachen, Germany, November 2012

Carsten Clauss, Simon Pickartz, Stefan Lankes, Thomas Bemmerl:
[bib] [url]
Hierarchy-Aware Message-Passing in the Upcoming Many-Core Era
In Grid Computing -- Technology and Applications, Widespread Coverage and New Horizons, InTech Europe, pp. 151-178, 2012

C. Clauss, S. Lankes, T. Bemmerl:
[bib] [url]
Performance Tuning of SCC-MPICH by means of the Proposed MPI-3.0 Tool Interface -- Poster Abstract
In Proceedings of the 18th European MPI Users Group Meeting (EuroMPI) 2011, Santorini, Greece, September 2011

C. Clauss, S. Lankes, P. Reble, T. Bemmerl:
[bib] [url]
Evaluation and Improvements of Programming Models for the Intel SCC Many-core Processor
In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS 2011), Workshop on New Algorithms and Programming Models for the Manycore Era (APMM), Istanbul, Turkey, July 2011

C. Clauss, S. Lankes, P. Reble, T. Bemmerl:
[bib] [pdf]
Recent Advances and Future Prospects in iRCCE and SCC-MPICH (Poster Abstract)
In Proceedings of the 3rd Symposium of the Many-core Applications Research Community (MARC), Ettlingen, Germany, July 2011



This research project is supported by Intel Corporation.